Mid frequency or power noise, respectively, is caused by switching events in high speed digital circuits and is causing voltage droops in the power supply. The magnitude of the noise depends on many different factors, which can be separated into deterministic components like packaging path, frequency, power supply path, capacitances between voltage and ground and statistical technology factors like leakage current, capacitor decharging process tolerances and aging effects, as well as workloads. The state of the art procedure to quantify the mid frequency noise is to measure on selected computer systems the noise via analog oscilloscope measurements and digital skitter circuits and worst case the margin for the voltage.
The disadvantage is a very conservative handling as the measurements on a few test computer systems do not give a representative description in order to derive a statistical evaluation and does not allow a feedback loop in a manufacturing system. Furthermore, this approach does not allow for an individual treatment of a specific computer system. A conservative power supply margin needs to be added resulting in higher power consumption and/or less performance/yield.
Furthermore, as technology features continue to shrink, power bus noise is becoming the dominant contributor to total timing uncertainty. High speed circuit switching may cause large, narrow current spikes with very rapid rise and fall times, i.e., large gradients in current. Voltage noise can also be very localized in its impact, depending on many factors such as the robustness of the power distribution grid. When the noise dissipates and the on-chip voltage supply later recovers, or even overshoots as the supply current falls, the circuits (buffers, gates, etc.) in these same paths speed up, returning to their nominal performance (with the normal stage delay) or even faster. The number of stages that can complete changes as the data path slows down or speeds up relative to the clock path.
In particular, such switching noise is an important component of total timing uncertainty, more even than skew or jitter (which are themselves affected by switching noise) or chip process variations. Clock skew and jitter, power supply noise and chip ambient and process variations may be considered the primary sources of timing uncertainty. In particular, the overall or total timing uncertainty is a complex combination of both clock and data path uncertainty that reduces the number of combinational logic stages that can be certifiably completed in any clock cycle and so, reduces chip performance.
In US 2005/0107970 A1, a circuit for measuring timing uncertainties in a clocked data path is described. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from power bus noise or jitter) in that progression. Skew can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
US 2007/0103141 A1 further describes a circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.